4x10 Gbit/s Capable Network Monitoring System: Planning and Implementation

OData support
Dr. Varga Pál
Department of Telecommunications and Media Informatics

The fast and effective transportation of Internet traffic is one of the major challenges of

the 21st century. To achieve the requirements of this challenge the network providers have

to thoroughly supervise their networks. This requires diagnostic and security monitoring.

Monitoring has become much harder as the bandwidth of the aforementioned networks

have been becoming exponentially higher. For example, the total annual traffic of the

Internet was 100GB in 1992, but in 2016 the total traffic was 26600GB per second. Most

monitoring tasks use purely software systems. Still, there are special high-performance tasks

that require hardware acceleration to work properly on-the-fly. FPGA is one of the popular

solutions for this problem. The versatility of FPGA devices makes them a lucrative choice,

but the cost of these devices prevented them from becoming widely popular. This paper

describes the design process of a very cost-efficient FPGA-based hardware accelerator,

the SGA-10GEQ 40Gbps PCIe (PCI express). The paper contains the description of the

design, implementation and test, and the challenges of this project from the viewpoint

of a hardware designer. The design step also includes a high-level optimization process

to achieve the goal of cost-effectiveness and the simplicity of the PCB design. The PCB

was designed with Altium designer CAD software. The whole design is my work from the

functional specification to the electrical tests, while consulting regularly with co-workers.

In the paper I emphasize the greatest challenges of this project:

10 different voltage rails are required for the FPGA and the high frequency peripherals.

10GHz metallic data transmission with high signal integrity.

DDR3 interfacing with the FPGA – is quite challenging because of the high bus

width and high frequency.

The selection of passive components, especially the selection of capacitors and the

optimization of bypass networks.

In the paper I also present the testing procedure, including the oscilloscope measurements

and the VHDL test core measurements.


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