In case of eliminating the errors of FPGA designs we use simulation or external test devices. These are perfectly able to handle simple designs with short examination period, but in more complex cases it is very difficult to see through the system, or we cannot even use them without peripheral devices.
The Xilinx Readback Capture makes it possible to do real time debugging on the FPGA using JTAG cable.
The most conspicuous advantage of this method is that we do not need complicated preparations to use it. With a minimal change in the design and the realization of reading from the device’s configuration memory, it offers a simple examination opportunity for the FPGA devices. The representation of the memory content we receive as an output, can be used with the files generated during the process of the configuration file creation. From this data, the system creates an output text file.
As an improvement, I started to study the possibilities of the method’s automation. This means the comparing of the previous output file and the simulation results. The finished program can oversee the process of simple designs, but it rather optimal for the verification of the Capture method, instead of automatic system surveillance.
In the thesis, I introduce the finished software and the basics to understand the use of Readback Capture.