Implementing an affine transformation IP using FPGA

OData support
Supervisor:
Szántó Péter
Department of Measurement and Information Systems

When the HD video and image display started to disperse, in favor of the better

image quality, the increase of the resolution became an expectation in the case of

the real time video signal processing. Because of the real time requirements most of

the signal processing steps can be achieved only by hardware.

The affine transformation largely covers – almost fully – the altering of the image’s

size, location and direction. For the implementation of the task it’s indispensable

for us to understand the mathematics of the affine transformation, to wit examine

the matrices of the affine transformation.

The FPGA (Field Programmable Gate Array) is perfectly suitable tool for making

the video signal processing with it. It can make it with the same high image quality,

in real time, so with tantivy velocity.

My thesis’s aim is to examine, how to achieve the real time video processing array

on an FPGA, which can do any affine transformation on the video stream which

comes on the FPGA’s input. First I will delineate the affine transformation generally

and the different image processing and filtering techniques. Then I will work out a

method for the affine transformation on the image processing area – from different

filtering techniques – in order to maintain the good image quality.

After it I will attain the designed algorithm in MATLAB environment. By the

MATLAB simulation I’ll make a proposal for a hardware system plan , which I’ll

implement in FPGA.

Finally I will delineate my achievements which I could make with the hardware

and make a proposal which parts of the hardware we could do further developments,

in order to enhance the bandwidth achieved by the hardware.

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