The modern, complex digital integrated circuits commonly operate synchronously. In these synchronous circuits a clock signal is necessary to synchronize the several parts of the whole digital circuit. This clock signal has to be distributed to everywhere on the chip and every synchronous subpart on the same local datapath have to recieve it in the same phase (with minimal clock skew). This is the main order of the Clock Distribution Networks (CDN). The problem is not obvious to solve, because the sizes of the modern chips are a few cm2 and the opertaional frequency reaches several GHz-s. This means that, the size of the chip and the wavelenght of the clock signal are comperable. Thus the concentrated parametrical approach can not be used to estimate the delays and also reflections and crosstalks have to be considered. Also a challenge to reduce the consumption of the whole circuit and of the CDN as well, because this is necessary for the proper operation.
In modern processors, reducing the operational frequencies of the temporarily not used subcircuits is an applied method to lower the consumption. In order to make the circuit capable to operate on different frequencies, adjustable frequency synthesizers have to be used (for example: Phase Locked Loop – PLL). Frequency dividers with adjustable division ratio are essential parts of these synthesizers. Low consumption, the ability to change the division ratio fast during the operation and robust operation is prominently important at frequency dividers.
For these new challenges, using Injection Locked Oscillator (ILO) circuits can be a solution. The ILO circuits appeared in the past decade and still an active field of researches.
In my degree thesis I present the architecture and operation of the CDNs and the frequency dividers used in the CDNs. I also present the ILO based frequency divider circuits that are designed by me. These circuits with additional digital circuits are able to perform frequency dividers with adjustable division ratio.