Application-Specific Instruction Set Processors in Smart Systems

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Supervisor:
Dr. Horváth Péter
Department of Electron Devices

Implementations for a given digital design problem can be of broad range, from application-specific circuits to reprogrammable processor or FPGA-based solutions. The former lacks flexibility and reconfigurability while the latter is not optimized for the specific task to implement. Application-specific instruction set processors offer a trade-off between these design parameters: their structure and instruction sets are tailored to best fit a given application area, but they also offer programmibility to some extent and therefore maintain flexibility. They can also have a special unit (accelerator) which can be changed from design to design with ease to further accelerate execution and reduce design time. As a great number of applications use trigonometric, exponential and logarithmic functions (such as DFT, DCT, Gaussian filters, PSK, robotics) my choice for the accelerator unit was the fast and precise calculation of these functions with the Taylor-series method.

Firstly a high-level model of the processor was developed in C#.NET environment, capable of simulating all functionalities of the processor with memories and other peripherals. Secondly the accelerator circuitry was designed in VHDL, and tested both in a standalone testbench and in the actual processor environment. After performance measurements a number of alterations were suggested, and a redesigned accelerator circuitry was presented. Finally a software equivalent of the accelerator functionality was implemented by the built-in instructions, therefore allowing for comparison between hardware and software-based solutions. A discussion on further design considerations ends the document.

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