High Level Modelling of Application-Specific Instruction Set Processors

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Supervisor:
Dr. Horváth Péter
Department of Electron Devices

The advanced production technology currently available in the semiconductor industry is bringing demand on raising the abstraction level of the design procedure. The widespread RTL design methodology might be complemented with high-level description techniques, however backwards compatibility is a mandatory feature to make the new approach successful. This paper demonstrates how to attach a functional unit described on the algorithmic level to the RTL model of a capable application-specific instruction set processor in such a way that the interface of the algorithmic level model is fitted to the RTL description instead of having to add glue-logic to the existing RTL to be compatible with a predefined standardized interface.

During this project, I used the elements of the SystemC library which can describe both RTL and algorithmic level models. To describe communication at a high-level I used the tools provided by the transaction-level modeling (TLM) part of the library. I have developed a so called transactor unit to the given interface of the microprocessor which describes the functionality of each of the protocols related to the interface. For demonstration I have attached an FFT C implementation to the RTL model of the microprocessor. Then, from the algorithmic-level description, I have manually modified the sources to create a scheduled model. To ensure that the developed models work I ran simulations by simply compiling and executing the source code.

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