FPGA based digital designs become more and more complex, so quick and effective design debugging is a key issue during the development cycle. Discovering run-time problems and verifying designs could improve developer productivity and the products time to market. The IEEE 1149.1 standard (commonly known as JTAG) could provide a great help to the debugging process. The JTAG interface can be used in many ways besides the debugging, it is widely used for communicating with and configuring FPGAs. That is the main reason for its availability on most development boards. Because of the previous reasons, the FPGA manufacturers provide a large variety of debugging tools, each for a different purpose. These tools are meant to serve general debugging needs, so an easily integrated, more area specific debug solution package could be an ease for the developers and the testers.
The first part of the thesis is about the JTAG standard and the debug tools of the most significant FPGA manufacturers. After that there is a documentation of my debug application, which is capable of uploading test data for the design, besides the runtime internal digital signal monitoring and controlling abilities. When driving out the test vectors, it is an important requirement that it must happen at system speed. Test data are stored in 2 dual-port, inferred block RAM, which works as a ping-pong buffer. That means that when we write to the first RAM, we can read the second, and the other way around. We must note that writing through the JTAG interface usually could be slower than the memory reading using the tested design’s clock. A counter generates the read address. I wrote the general purpose debug module’s design in Verilog hardware description language.