The extraordinary growth in design size and complexity continues to make the process of design verification a critical bottleneck for integrated systems. Limited access to internal signals, advanced FPGA packages, and PCB electrical noise are all contributing factors in making design debug and verification the most difficult process of the design cycle.
The purpose of my thesis work was to design a general purpose logic analyzer that can be synthesized for ASIC and FPGA technology, respectively.
During the first semester of the thesis work, I got to know the different FPGA and ASIC architectures, I compared the standard cell ASIC design with FPGA design and I summerized their main differences. I also got to know the design debug techniques for systems based on FPGAs, including the RTL simulation method, the use of internal and external logic analyzer and real time debug devices produced by the two big FPGA manufacturer (Xilinx, Altera).
During the second semester of the thesis work, I implemented the logic analyzer modules in VHDL, I did the functional verification using testbenches, and finally, I synthesized the final logic analyzer in a Cyclone II FPGA, which was on an Altera DE2 development board, and I tried to solve the communication problems between the logic analyzer and the third-party software.