Design of analouge CMOS frequency divider circuits

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Supervisor:
Dr. Bognár György
Department of Electron Devices

In my thesis work, I deal with the research and development of a novel local clock distribution center, which is one of the most important subcircuit of the clock distribution networks. The recent large scale integrated circuits are synchronous implements, therefore we need to provide the accurate clock signal for them. Due to the fact that the modern UVLSI circuits run in high frequency (more GHz) and measure a few cm2, it is a real difficulty to get along the clock signal to the registers simultaneously. If it doesn’t happen, functional error occurs. Reducing the dimensions, the delay becomes greater, because of the increased side capacity (T = RC). To solve this problem, we have to place the component circuits (ALU, controller circuits) close to each other and build up a clock distribution network. Over the years, many solutions have been found to distribute the clock signal properly. In this work, I present the structure and operation of the CDNs (Clock Distribution Networks) used in VLSI circuits and SoC (System-on-Chip) systems in detail. The new circuit is based on an analog frequency divider, which consist of an ILO (Injection Locked Oscillator). Section 2 describes the structure and operation of frequency dividers, and the injection locking phenomenon. Hereinafter I review and describe the implementation opportunities of the target circuit in detail and I present the steps of the design of my novel implementation as well as the simulation results. I design the circuit with the Cadence IC 6.1 design software in 0.35um AMS technology. I verify the correct functional operation with simulation results.

The new circuit I designed as a result of my research and development work is a low-power frequency divider which is able to synchronize to a clock signal and broadly applicable.

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