The topic of my master's thesis is to design a readout circuit for a capacitive humidity sensor with the sensor's capacitance as its input and the measured relative humidity in a digital form as its output.
This is a complex circuit design task which includes the design of the analog integrated circuit to determine the value of the capacitance of the humidity sensor, the design of the layout of this circuit and the design of the circuit for digitalisation using a HDL language.
At first I had to decide what kind of method I should use to measure the capacitance and what kind of circuit components are necessary to realize it. Then I designed the induvidual components and discovered the sources of errors that can possibly cause trouble during operation and optimized the components to fulfil the criterias defined by the specification.
Next, I created the layout of the circuit following the layout design rules, that are destined for minimazing the effects of the uncertanties of the manufacturing technology.
Finally I designed the digital circuit using verilog leangue, that samples the output signal of the analog circuit, stores the data in digital form and transmits it via series communication protocoll. It is also able to correct some of the errors of the analog circuit increasing the accuracy of the determination of the relative humidity.