In digital systems signals can possess unwanted states because of their electronic structure and the hazards caused by signal transitions. In theory these can be eliminated, but in practice this is almost impossible even in not too complex systems. Therefore instead of assuring that the signals are proper in every moment, they are only sampled when they are certainly stable.
In synchronous systems (that are nowadays mainly used) the validity of the signals is determined by a global clock signal. Thus we assume that time is discrete, therefore the planning of timings becomes easier. Using an appropriate clock period the hazards and the dynamic state of the circuit elements can be ignored. Design of synchronous systems is aided by mature synthesis programs, that generate the desired logic from the high level input.
In synchronous systems, many problems can arise, for example, the clock skew in distant parts of devices, the resource demand of clock generation and distribution and that the maximal clock frequency is determined by the critical path. These disadvantages might be avioded by globally asynchronous devices (that are locally synchronized with handshaking protocols).
During the semester, the efficiency of an asynchronous FPGA was examined. Using simple elements, the operation and properties were compared with a conventional device, and I have designed a simple Ethernet loopback module.
The ultimate goal of the masters thesis is the implementation of Ethernet connection and performance testing of the FPGA with a signal processing algorythm.