Advanced processors released these days use a technique called instruction pipelining to improve instruction throughput. However pipelining introduces a set of problems, one of them being the control hazard. To resolve control hazards the outcome and the target address of the branches must be predicted. According to my measurements every 6th--10th instructions are affected, thus even a small improvement can make a huge difference in the execution time of programs. In my thesis I measure some branch prediction algorithms in use, and benchmark them using data gathered from real life applications.
some of them use interpreters to execute code. By investigating the Lua interpreter I show how much improvement in speed can be achieved by just using a better branch predictor in the CPU.