Nowadays programmable logic devices get increasing part in hardware production, so do FPGAs. The main advantage of FPGAs (Field Programmable Gate Array) is the high number of usable logic gates and the relatively great freedom of connectivity. This is a great advantage in developement, since bigger and more complex systems can be implemented on FPGAs. During the developement process the designer uses a HDL (Hardware Description Language) language to describe the specified functionality. From the HDL code a synthesis tool generates the code programmable onto the chip which contains the used gates and their connections, the netlist.
However this developement causes difficulties for the designers, too. There is a competition in the market of synthesis tools. Not only the hardware poducers but independent companies also develop such softwares. Besides more hardware producers offer their own FPGAs in which they integrate more logic gates and special functions, like memory blocks and arithmetic blocks. Not all the synthesis tools can use all these blocks at maximal efficency. The same design may require several times more resources than the optimal number if not synthesised by the correct tool.
The hardware and software producers also studied this issue. In my thesis I will study their results. My goal is to develop a framework that can synthesize the design by using different synthesis tools, compare their results and can give feedback to the developer about the results of each tool. By doing so, the developer can easily overview the results and can descide which tool should be used with the current design.