Binary CNN implementation using FPGA-s

OData support
Supervisor:
Dr. Fehér Béla
Department of Measurement and Information Systems

Neural network based appllications demand significant computational power. The dominant hardware platform for these computations are graphics processors, which are capable of executing a large number of parallel operations. Unfortunately in most cases they can not be used in embedded systems due to their high power requirements.

The complexity of the operations necessary for neural networks can be reduced by decreasing the numeric representation's precision. Using the proper methods, these simplifications can be made without a significant loss of accuracy. The extreme case of quantizitaion is the use of binary numbers, which allows for the application to be executed on alternative platforms as well.

The aim of my thesis is the implementation of a binarized convolutional neural network on a heterogenous hardware platform. The system benefits from the FPGA platform's parallel computational capabilities as well as the advantages of high-level programming languages used on microprocessors.

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