The CAN bus is one of the most popular serial communication protocol. It is widely used due to its robustness in high demanding environments for example medical imaging systems discussed in this paper. Usually, if CAN is not supported by the chosen controller, an external hardware is used to connect the CAN to the system.
In this paper i design a CAN interface to FPGA as an IP module, because in these systems the FPGAs are necessary elements anyway. So, by abandoning the external hardware, we can reduce the amount of electronic elements, save cost and reduce complexity.
In my paper i am going to introduce how the CAN works, discuss the CANopen standard. I describe the properties of the communication, the ordinary concept
I am going to design the block diagram of the CAN controller, introduce a solution for handling the packets. Based on the block diagram I'm going to make the detailed hardware plan and implement it in VHDL/Verilog languages.
I am going to use simulation to check the design.