Previous studies reported, that DDR3 memory retention can be estimated using memory error verification using modified refresh period.
DDR3 JEDEC specification defines that each cell must be refreshed in every 64ms. This time period is too short to see the data loss of the weak cells. However, with increased refresh time period (1-10 sec), the weak cells become ‘visible’, by losing their data.
The main goal of the DDR3 memory retention analysis is to create better memory life time estimations using the result of the retention measurements.
To measure the memory retention I used a Virtex 6 FPGA based evaluation board from Xilinx. With the appropriate modification of the Xilinx MPMC memory controller I was able to change the memory refresh interval freely.
During the retention analysis I focus on 3 types of measurement. I measure the number of memory errors with modified refresh interval using:
• memory modules at room temperature
• memory modules at high temperature (40°C - 80°C)
• previously temperature stressed modules at room temperature. The temperature stressed modules have similar characteristics, than the modules used at
normal operational conditions for many years (naturally aged modules)
The final aim of the investigation is to create a procedure, which can help to estimate the lifetime of the DDR3 memory modules during the end production check.