In this thesis my task was to create a module, which can be connected to the interface of a DDR4 bus functional model. By using this module I had to verify the bus functional model. The first step was to create my module using the DDR4 standard. My company consultant specified a set of the main functions which I had to verify, and my module had to handle these functions properly. After the creation of this module, the next step was to build a verification environment around the bus functional model. At this point it was important to make everything automatic for the future test. Following this, I specified what test cases are necessary to verify the proper behaviour. I created 12 tests, where I used as much random generated numbers as possible. All these test are proved the expected funcionality. For the last step of my work I run a regression on one complex test case, to make sure, that the system is working good with numerous randomly generated values. The result of the regression was clear after mor than 100 runs of the test case.