My thesis is to analyse that the DSC compression by VESA could be implemented within FPGA. My thesis goal is to give plan that how the DSC compression can be implemented by VHDL language. The thesis contains the estimated required resources and the simplifications.
The DSC compression is a visually lossless real time video compression standard. In case where the task requires that the required bandwidth decreases, nowadays we need to use real time compression because in the vast majority of embedded technologies have not “enough” resources to store a video, so we can’t use the not real time compressions.
The main goal of DSC is to be a widely used real time compression. The greatest advantage of the DSC over other procedures is to use less resources. This is the main reason that DSC may be suitable for an implementation by VHDL language in FPGA.
In the first half of my thesis I have written the basic properties which are used by the video compressions. I have presented in detail the DSC’s operation. I have showed the DSC’s sub-operations as I had organized at implementation.
In the second half of my thesis I have presented, that how the DSC’s sub-operations can be implemented by VHDL language. These modules need to be verified by software, because most of the modules are signal processing modules so the test is not effective by hand. I have showed the test environment which I have used to verify the modules. Finally I have introduced how the IP could be integrated.
The thesis gives a plan that how DSC 1.2 encoder can be implemented in FPGA (optimized at 4K@60Hz).