Implementing de-interlacer in FPGA

OData support
Supervisor:
Szántó Péter
Department of Measurement and Information Systems

Since the invention of the television, displays have been developing rapidly. There is a continuous demand for appliances with better and better picture quality. However, processing and displaying an interlaced signal that was introduced at the beginning of television causes several problems for these displays, such as interline twitter or combing.

The aim of my thesis is analysing deinterlacers, which offer a solution to these problems, and the design a feasible algorithm, and analysing its realization using FPGAs.

This paper briefly summarizes the standards used for television broadcasting and discusses the interlaced format with its advantages and drawbacks. It, then, reviews the role of the deinterlacer and the basic algorithms used, along with their advantages and disadvantages.

Then, the process of designing a feasible algorithm for FPGAs and the results of this development process are presented. Finally the FPGA implementation of the designed algorithm is presented.

Downloads

Please sign in to download the files of this thesis.