Implementing a deinterlacer core on FPGA

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Szántó Péter
Department of Measurement and Information Systems

The interlaced scanning was the common method in the age of cathode-ray tube televisions, which means that the odd and even lines of a frame have been refreshed in a different time. The fields also have been recorded in different times in order to motions appear continuous. This provided a solution to several problems, but still its biggest advantage is reducing the required bandwidth by half.

Televisions have appeared based on new technologies thanks to the development of science, and they use progressive image scanning already. A number of problems encounter if we try to play an old video recording on a new display such as interline twitter or combing. Deinterlacer algorithms try to find a solution to these problems.

The goal of my thesis is to create an FPGA based deinterlacer, which provides a good quality and requires few resources.

In the first part of my thesis I present the fundamentals of video technology, and I introduce some widespread deinterlacer algorithm also. I prepared this algorithms’ MATLAB simulation, I present the results of this.

In the second part ready-made deinterlacer realization will be presented. I introduce the theoretical knowledge which is needed to design the hardware as well as the problems and their solutions which came up during the implementation.

Finally, I will summarize the results of my M.Sc. thesis and make a proposal for the opportunities of further development.


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