During the semester I was working on the implementation details of a 16QAM demodulator.
My goal was to acquaint myself with the theory, and difficulties of digital demodulation, and to design a hardware solution, which uses FPGA resources economically, whilst being capable of high speed operation. Thus, I achieved, using the high degree of parallelism in FPGA-s, that the design is capable of processing signals at tens of MHz of symbol rate. Because each symbol codes 4 bits, that means a few hundred Megabits of throughput can be achieved. I strived to design a system, which would be capable of coping with real world conditions and didn’t ignore the non-ideal effects present in the transmission channel, or the receiving or transmitting devices, such as Gaussian noise and phase delay in the channel, the distortion of carrier frequency, due to the Doppler effect or other natural causes. Also I took into account the phase, and frequency difference between transmitting and receiving the symbol clocks , and I did the sampling of the signal according to this estimate.