Realizing a digital filter in ASIC and FPGA version

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Supervisor:
Dr. Gärtner Péter
Department of Electron Devices

One of the most basic elements of digital signal processing (DSP) is the digital filter, which can be used on a bandwidth-limited signal to pass or attentuate certain parts of its frequency spectrum. Nowadays they appear in nearly every field of technology and are very well suited for sensitive measurements, such as the ones performed in medical science. The goal of my work is to realize a low-frequency low-pass finite impulse response (FIR) digital filter, which is capable of filtering signals measured in an electrocardiographic monitoring. The starting point is the verilog hardware description language (HDL) code of the filter already specified in my project laboratory subject. With proper methods I transform this code into a format which becomes synthesizable. During my work I realize the filter by following two types of design flow, the first being an ASIC design and the second as an implementation on an FPGA. For verification I use simulations on the ASIC layout, and for the FPGA realization I test it with a visual display of a real ECG signal on a VGA screen for which I build the testing environment myself.

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