Design and Implementation of a Resource-efficient TCP-stack for FPGA-based Devices

OData support
Supervisor:
Dr. Varga Pál
Department of Telecommunications and Media Informatics

For the development and operation of core networks with application-based functions (e.g. the LTE Evolved Packet Core), it is important to know the amount of traffic the devices can safely handle. Therefore, in addition to the functional and integration tests are one of the most important test of endurance, or mass-testing.

Nowadays biggest Internet traffic – including mobile traffic – is generated by the Facebook and Youtube applications. The emergence of these patterns were amplified by the quality of service (QoS) and the quality of experience (QoE). In this case TCP, the protocol providing reliable data transfer, is widely supporting the necessary transport functionality. Therefore, the effective mass-tester should be able to generate and manage TCP-based traffic. The tracking of parallel TCP streams, however, is very resource-intensive task: in this case, at least the tenfold amount of parallel stream counterparts required to be controlled at high speed. For this, hardware support is needed: the FPGA-based [2] (Field Programmable Gate Array), low level programmable network devices have proved their worth in similar applications.

The great network speeds along with the high paralleling demands require hardware access protocol, whereas these provide delay-free and reliable data transfer as well. Therefore the task is the design and implementation of a TCP traffic generator module which can operate inside of a FPGA, in many instances. Unfortunately, the TCP connection and maintenance has relatively high resource requirements. This is because the in-order and packet loss-free data transfer demand. This could cause serious difficulties when generating traffic in a large amount of parallel connections.

In my thesis, I am going to introduce a TCP implementation for an FPGA from the family of XILINX VIRTEX-5 [3] During the process it was very important to cover the most important functions defined by the TCP standard [1] Obviously, the initial challenge was to find the "unnecessary" features and take advantage of leaving them. As a result, I have specified, designed and realized stripped down TCP variant.

[1] RFC 7414 - A Roadmap for Transmission Control Protocol (TCP) Specification Documents, 2015, https://tools.ietf.org/html/rfc7414

[2] The Xilinx FPGA official site: http://www.xilinx.com/training/fpga/fpga-field-programmable-gate-array.htm (status: September 2016.)

[3] The documentation published by Xilinx for Virtex 5 FPGA family: http://www.xilinx.com/support/documentation/data_sheets/ds100.pdf

(status: July 2016.)

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