Design of Ethernet analizer using FPGA

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Dr. Fehér Béla
Department of Measurement and Information Systems

The rapid development of network technologies, and the growing number of users make great demands to network systems. With the increasing number of newer applications, higher demands have to be met. Problems can arise due to the system complexity, and in most cases they only can be solved by examining the datastreams. The network analyzers are connected to the pysical layer, so they are able to see all the frames, and by analyzing them the reason of the failure can be found. In my dissertation I realize an Ethernet analyzer on an FPGA chip, where the user is informed about the types of frames and statistics concerning to packets travelling on the network. For building up the system the Spartan-3A DSP S3D1800A board was used. The Ethernet packets are processed outside the microprocessor system, in the custom peripheral. The test was performed by looping back the PHY chip. The frames are processed by hardwer modules in a layered way, and depending on the content, bits in status registers are set. The resulting system is functionally quickly and easily extensible, the one of the most popular feature of analyzers, the network discovery can easily implemented.


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