Filters are used in many applications for reducing the CPU load so that only appropriate Ethernet packets will be forwarded. In many cases, it is enough to check some byte fields. This function is provided by commonly used filters. Berkeley Packet Filter (BPF) makes more complex and flexible filter conditions available (based on arithmetic, compare and jump operations).
The goal of my thesis is to create a hardware in an FPGA circuit, which can execute BPF filtering on Gigabit Ethernet dataflow.
In the first part of the thesis I present the details of the Ethernet and Internet Protocol (IPv4) standards. I briefly describe two available products on the market which use packet filtering among others. After that I discuss the structure of BPF filtering, including the variables and possible operations.
I created a Java compiler to transform BPF operations into machine code. I present the structure of the hardware design which I implemented and I describe the details of the different modules. External memory is necessary to store packets which means bigger latency in reading, thus I implemented a cache to hide this delay. Fragmented IP packets can be reassembled and filtered with limitations. Finally, I delineate some possible further developments.