Soldering of QFP components having exposed pad.
Summary of the Diploma Project of Bence Kohári
A QFP or Quad Flat Package is a surface mount integrated circuit (IC) package with "gull wing" leads extending from each of the four sides. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common. QFN or Quad-Flat No-leads is another type of package where perimeter lands on the package bottom provide electrical connections from the IC to a printed circuit board (PCB). Some QFP and most QFN packages have an exposed pad, which is an extra pad underneath or on top of the package to improve heat transfer out of the IC usually into the PCB. The pad is typically 10 or more mm², and with the pad soldered down onto the ground plane, heat is passed into the PCB. Heat transfer can be further facilitated by metal vias from the thermal pad into the large copper inner layer (ground plane) of the PCB. In addition that the exposed pad serves as a heat sink for the package, it also gives a solid ground connection.
In my case the test QFP and QFN packages had 144 and 48 pins with 0.4 and 0.5 mm pitches, and both packages had exposed pads of 7.5 x 6.74 and 5.2 x 5.2 mm2 sizes with 0.1 and 0.05 mm stand-off heights, respectively.
A particular concern for the soldering of exposed pads of QFPs and QFNs to the PCB is the formation of inclusions and voids which might reduce the heat dissipation capability of the joint. Voiding is caused by the application of insufficient amount of solder paste or by the migration of the molten solder into the thermal vias driven by the capillary effect.
In my diploma project I had to find the optimum solution for producing problem-free solder joints using the given QFP and QFN IC packages. For this aim, I made a Design of Experiments, which included the design of a test board, assembling and soldering the IC packages to the board, and testing the joints by X-ray and optical inspection methods. The test board was designed to analyse the following void reducing methods and their combinations:
• reducing the number of via,
• applying smaller via diameters to reduce the amount of migrated solder,
• eliminating the via filling by solder mask tenting,
• applying divided thermal pads to allow flux degassing,
• placing the vias into the spacing of the divided thermal pads, where no solder paste is printed,
• applying solder paste overprinting beyond the thermal pad onto the solder resist in order to increase solder paste volume,
• increasing pad size on the PCB, pushing the vias into the enlarged area, covering them by solder resist and applying solder paste overprinting onto this area,
• applying solder preforms of different sizes, placing them onto the pads before IC package placement.
The application of the very expensing step-stencil method was excluded; however a relatively thick stencil of 130 µm was used. When three test boards and the stencil were manufactured for me, I assembled the boards by applying SAC 305 lead-free solder paste stencil printing; placing the ICs by automatic pick-and-place machine or by the manually operated Fineplacer; carrying out the soldering by vapour phase soldering; and testing the joints by X-ray and/or optical inspections.
On the basis of the results of the experiments, the following two methods are recommended for reducing void formation at soldering exposed pads of QFP IC packages:
• applying exactly calculated volume of solder paste overprinting ensured by the proper aperture size of the stencil, thus allow filling up the thermal vias as well as the stand-off under the IC;
• using a solder preform with well-defined dimensions, placed into solder paste printed along the perimeter of its body, thus providing proper amount of solder and flux for joint formation.
Regarding the QFNs, the results showed that the application of the 130 µm thick stencil ensured the formation of voidless and proper solder joints for both the thermal pad and the terminal lands.