Design of an FPGA based JTAG test controller unit

OData support
Supervisor:
Dr. Fehér Béla
Department of Measurement and Information Systems

The advanced state of manufacturing has been followed by fast and easy-to-solve automated test as a key problem. In this topic, IEEE 1149.1 standard, also known as JTAG has a well-formed functionality. In the last two decades, beside discovering manufacturing faults its scope has been expanded e.g. by debugging or communication with programmable devices (microcontrollers, FPGAs). JTAG serial data line has daisy-chain architecture, the devices connected to the boundary scan controller form a chain. As manufacturing of printed circuit boards is developing, there are denser and more complex solutions which result an extremely long chain and what is more, programming an FPGA. In these cases, configuring the chain, modifying it to the actual task can significantly shorten the time required for the test cycle and can solve problems such as detachment while using more different power supplies. Integrated circuits called JTAG multiplexers (a.k.a. scan bridges) have been designed for these functions.

My work began with getting to know the IEEE 1149.1 standard, understanding of basic elements, architecture and operating mechanism was important during designing. There are several multiplexers on the market. I gathered the main features that are required from such a device and I added wants users have been missing. I developed in Verilog hardware description language, the JTAG multiplexer can be implemented in FPGA. Its functionality can be modified easily if needed for optimal application. The development was led on continuous simulation and also measurements were done in order to verify my work.

Downloads

Please sign in to download the files of this thesis.