Nowadays the use of packet switched transfers is spreading increasingly in the area
of telecommunication. The backbone network of telephony is rather become packet
switched network, including Ethernet, too. The holders and providers of networks
need devices, which are able to make transition between traditional TDM (Time
Divison Multiplexing) circuits and Ethernet networks.
FPGAs (Field Programmable Gate Array) are suitable tools for making complete
systems which are capable of multiplexing more TDM channels into an Ethernet
network. Synchronizing and clock recovery methods can be implemented in the
FPGA-s for synching TDM connections.
My thesis briefly reviews those TDM networks which are used for traditional voice
transmission, and the Ethernet. Following the review I explain the structure of TDM
over PSN (Packet Switched Network) in more detail.
The next section discusses a system design for implementing a PDH over Ethernet
unit outlined by me. After, I specify a clock recovery solution that is used for network
Next, I detail the structure of the hardware design which I have implemented in
Verilog language for FPGA-s.
Lastly, I describe the resource requirements of my hardware and outline possibilities
of how could this system be improved in order to utilize the bandwidth of the
Ethernet network effectively.