Development of an FPGA network interface

OData support
Supervisor:
Dr. Fehér Béla
Department of Measurement and Information Systems

Nowadays a lot of devices connect to the Internet or to other networks. The complexity of these devices has a very wide range from high performance servers to simple embedded systems. The complexity and the costs are a relevant consideration when designing an embedded system.

The goal of my thesis is to design an FPGA logic network of a MAC network interface. With the interface a soft core embedded processor will be able to send and receive Ethernet frames over a network. My aim was the simple realization and keeping the costs as low as possible, therefore the MAC unit supports only the most necessary services. The MAC unit connects with Wishbone bus to the soft core processor, and is able to communicate at 10/100 Mbit/s data rate over a point-to-point Ethernet network.

At the beginning of the thesis I explain the operation of the TCP/IP networks and the tasks and protocols of a MAC unit. After this I describe the designed MAC unit and its operation. Finally I present the simulation of the operation of the MAC unit.

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