Design and characterization of digital circuits of FSK RX-TX chain

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Supervisor:
Dr. Bognár György
Department of Electron Devices

My task was to design the digital baseband circuits of an FSK (Frequency Shift Keying) RX-TX chain and to create models of its certain analog circuits in the digital domain. To design the given system it was necessary to get an overview of the theoretical background knowledge based on the related professional literature. In my thesis I summarize the more important ones from the theoretical backgrounds related to my work. In connection with the latter I present the basics of the FSK modulation and the theoretical background of the quadrature signals. Furthermore in my thesis I review the basics of the design of the digital filters, during which discussion I mention the more important background kowledge related to both the FIR (Finite Impulse Response) and the IIR (Infinite Impulse Response) filters. I place a special emphasis on the description of the IIR filters, because in the designed system IIR filters were used. In my thesis I outline the things to know about the fixed-point number representation, too, within the framework I present the effects of the fixed-point number representation, the characteristics of the fixed-point arithmetic, and the topic of the quantization noise. I expound the classification of discrete-time signals according to their energy and their avarage power, as well as I discuss the definition of the bit-error rate’s concept.

In the system there is a modulator-demodulator pair, and the logic model of the noisy channel, which connects them. The aim was to implement the system on FPGA, for which it was necessary to create models of the system’s certain analog circuits in the digital domain and to design the system based on a hardware description language (SystemVerilog). To help the test of he system implemented on FPGA a test environment had to be designed which was implemented on the FPGA, too, and which contains the system under test, executes its testing, and with the help of a terminal running on a PC, it can be contacted through an UART interface. With the help of the latter, different commands can be issued to the control logics which can be found in the test environment, for example: the set of the individual parameters of the system under test, the start of a BER (bit-error rate) test, the read back of the results of the BER test.

Before the design of the system’s implementation based on a hardware description language the floating-point and the fixed-point Matlab models of the system had to be designed which served as a reference for the system’s implementation based on a hardware description language in the later stage of the work. The results of the simulation carried out on the implemented system were compared to the results of the simulations carried out on the Matlab models, so the adequacy of the previous one to the requirements based on the Matlab models could be checked. During the simulations carried out on the floating-point Matlab model I simulated BER tests, too, of which results I compared to the results of the BER tests carried out on the system implemented on FPGA.

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