There are two different hardware description languages, which are used almost any time, the Verilog and the VHDL. Both of these two languges are perfect for modeling digital systems and logical functions as well, however the resulting models’ correctness has to be verified and checked. That’s why, they often use another descripting language, a hardware verification language, which provides all the functions that demands precizity and profound verification procedure. The SystemVerilog language uses a lot of syntactical elements from the C and the C++ programming languages, because of this it supports the systrem-level designing and verification processed in one single description.
I would like to demonstrate with my thesis that the SystemVerilog, wich is mostly used verificaton purposes, also capable of synthesing digital systems. In my work, I used the SystemVerilog language for describe a model of a digital electric circuit, which can leading any number of elevators. I have choosen this field because in my humble opinion the lift guidance is a sufficient hard problem to it’s solution makes a challenge.