Automatic VHDL generation from algorithms given in functional language

OData support
Dr. Arató Péter
Department of Control Engineering and Information Technology

Although the working speed of the conventional processors is growing continually, there are a lot of problems that are too time-consumptive like

biological or physical computing and that’s why they have to be run in a more efficient hardware structure and sometimes in special hardware for the exact

problem. Usually, these hardware structures are written in HDL (Hardware Description Language), that are not so well-known by the mathematicians and IT

engineers, they usually write the algorithms in generic programming languages. Writing a problem in HDL or in generic programming language is very different. To overcome this gap, there are a plenty of researches that are very important parts of the so called System Level Synthesis.

The aim of my essay is to work up and implement an HLS method, where the source code is a functional language code describing the algorithm. I focus on the Haskell language, because it has a very powerful development and a large developer community, and it supports the research works well.

The advantage of my method is to generate the VHDL description of an FPGA from the restricted Haskell source code automatically. I use the elementary operation graph (EOG) as an intermediate representation, which is a homogenous synchronous dataflow graph (HSDF). In my essay I discuss the compiling steps of the single-rate and the multi-rate algorithms separately.

For this work I use existing open source software such as the Glasgow Haskell Compiler (GHC) program, because the frontend of this compiler generates a

structure that can be processed easier than the original source code. The program I developed generate the VHDL code from this transformed structure

automatically. In the compiler sequence we can insert a pipeline optimization stage, like the PIPE design system developed in the Department of Control

Engineering and Information Technology.

To compile the code in user friendly way, an integrated development environment is needed. For this purpose I developed a framework based on Eclipse, so we can edit the source code, view the intermediate graphs and can generate the target code in the same CAD software in a beneficial way.

I demonstrate the functionality of the method using practical examples like a PID controller and a part of the MP3 decoding algorithm.


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