Gigabit Ethernet interface design with Xilinx FPGA

OData support
Supervisor:
Dr. Koller István
Department of Networked Systems and Services

The goal of my thesis was to create a system, capable of receiving a high-speed continuous stream and streaming it over Gigabit Ethernet.

The system was implemented on a Xilinx Artix-7 FPGA on an AC701 Evaluation Board. Data is provided by a 32-bit counter. To move the data, I used Xilinx IP core DMA engines with AXI4-Stream bus interface between the counter, memory, and Ethernet MAC. The main control unit of the system was a MicroBlaze soft processor with an AXI4-Lite bus interface. Communicating with the Ethernet PHY was implemented by a Gigabit Ethernet MAC Xilinx IP core with an AXI4-Stream bus interface.

I implemented data transfer, using UDP protocol. Ethernet, IPv4 and UDP headers are generated by the MicroBlaze soft processor.

The continuity of the stream transmitted via the Ethernet media was verified during the test phase.

In my thesis, I present the system I designed, and particularly its modules. At the end of my thesis, I examine the required resources for a 10 Gbit/s system.

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