HDL module verification using a general UVM framework

OData support
Supervisor:
Kis László
Department of Control Engineering and Information Technology

Nowadays, due to the market competition has become important, that in the purchased devices - in addition to the software updates - the hardware can be also modified. FPGA technology plays important role in this. For FPGA development different HDL programming languages are used. The module verification has improved a lot in recent decades. The appearance of OVM and UVM was an important event of improvement, since then a lot of development companies have started to use these SystemVerilog based, object-oriented methodologies. The growing demand for Verification IPs shows, that verification has become more and more important.

In my thesis I constructed a general class hierarchy, which speeds up the verification process and makes it easier. The developer can build up the test environment by setting the configuration parameters and implementing some virtual methods in derived classes. The class hierarchy also supports using external VIPs. The functionality of general class hierarchy is presented through the verification of Smart Card Controller module.

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