The purpose of this paper is to search for and try out new verification techniques that can be used to keep up with the ever-growing complexity of recent hardware architectures.
In this context I introduce the UVM verification methodology based on the SystemVerilog language and its feature of coverage driven constrained-random tests.I also build a verification environment made out of UVM components around the to be verified design.
This verification methodology has 3 basic pillars that I focus on:
- Constrained random stimulus: Random nature of stimulus allows testing a wide spectrum of functionality of the DUT.
- Correctness: The behaviour of the DUT induced by the tests should be checked. This is done by built in automatic checkers as well as protocol checkers where a communication protocol is implemented between elements.
- Completeness: Testing can only be complete when all the defined coverage requirements are met by the tests.
For further improvement I research and show the basics of machine learning. Using reinforcement learning I managed to optimize the constrains used by the random constrain tests with goal of maximizing the functional coverage. After plotting the results of the algorithm I point out the advantages and disadvantages of the program and the verification environment.