In my dissertation I implement a Hardware-In-The-Loop system being able to model the behaviour of an electric drive. The drive model consists of a 3-phase rectifier, a DC link, a three-phase two-level voltage inverter and an asynchronous machine. The model works both functionally and is also able to model such secondary functions as semiconductor losses, transistor dead times and saturation of the asynchronous machine.
I build my model using Matlab Simulink toolbox elements in such a way, that the Verilog code - generated from the model - can run on the Xilinx Zynq-7000 platform. I need to generate a bitstream using Matlab and Xilinx Vivado, furthermore the model needs to be suitable for a fast file generation for the FPGA. This is essential, because it speeds up the development significantly.
I create a Matlab application to control this FPGA based, real-time drive simulator, on which I also carry out measurements.
At the end of my dissertation I present the capabilities of my system and what it can be used for during the development of a drive control system.