During the semester I have continued my studies, works that I made in the Project Laboratory course. Within the confines of this subject I have learnt the purpose and the advantages of high level synthesis, and also the emerging problems during the design. My research focused on the loops in the system, moreover the difficulties which appear because of them.
I have become acquainted with the functions and the modular structure of the DECHLS high level synthesis tool made in the Department of Control Engineering and Information Technology. My goal is to improve this by making new modules, so that the program could handle the loops in a better, more efficient way, therefore increasing the throughput and the parallelization of the designed system by partitioning the bigger loops.
The program written in C language can find the loops in the C source code, identify them, build a binary tree according to how they are nested inside each other, so the designer could divide the loops into smaller pieces to the given depths.
The other module partitions the loops according to the loop-hierarchy and the parameters. The modified C file is the output of the program, this remade file will be the input of the DECHLS tool.
As the conclusion of my work I have tested the modified programs, measuring the run time of the original and the modified software on a general purpose processor capable of parallel execution.