Time-critical tasks are often handled by hardware accelerators in networking equipment. FPGA (Field Programmable Gate Array) devices enable wiring hardware elements inside the chip, through programming. FPGAs are used to cover various tasks – including packet-filtering and protocol control – in modern, packet-switched networking equipment. There are some specialized systems built especially around FPGAs, in which all networking functions have to be implemented in FPGA, including the handling of device- and network management protocols, as well.
The ICMP (Internet Control Message Protocol) is widely used for testing the reachability of networking devices by ping. The current thesis project is aimed for planning, development and verification of such an ICMP-handler module, which is implemented inside FPGA, and which is able to work efficiently at a high-speed, 100Gbit/s Ethernet platform, as well. One of the key requirements during the development was that the solution has to be easily integrated into networking equipment that is implemented in VHDL (Very High Speed Integrated Circuits Hardware Description Language), and built on XILINX Virtex-5 or Virtex-6-based platforms.
The thesis project was planned and developed within an already available framework, which allows the implementation of various protocols inside FPGAs. This special framework follows the basic principles of the OSI (Open Systems Interconnection) model: it consists of layers supporting each other in a hierarchy. Beside this, it provides an instrumentation for universal handling of PDUs (Protocol Data Unit) and IDUs k (Interface Data Unit), hence supporting the implementation of various protocols in VHDL.
During this thesis project, I created an ICMP protocol-realization connected to the provided framework, and then carried out various measurements with network management information processing tools, in order to validate the implementation.