Nowadays, the different usage of telecommunication applications requires high complexity systems. Ones which are able to perform high speed operations and high level parallel functioning. To satisfy both we should use the ideal combination of CPU’s for high speed, and FPGA’s for paralleled operating at the same system. But there are other parts of this kind of complex systems, for example peripheral devices or memories. To manage the connection between the elements, we should use communication protocols, which are responsible and well defined for communication quality. Furthermore the systems speed depends on it.
In my thesis work, I designed an Integrated Flash Controller interface based on the standards of Freescale, which is used for achieve communication between a Freescale processor and an Altera FGPA.
In the first part of my thesis, I collected the necessary information about the Freescale communication processors and about the contained memory controllers. After that, in the second part I designed the interface following the steps of the general FPGA design flow. My ambition was to learn the basics of the communication protocol implementation, whereby I’ll be able to use this knowledge for designing multiprotocol systems on FPGA in the future.