IP Packet Processing by Manycore Processors

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Supervisor:
Dr. Cinkler Tibor
Department of Telecommunications and Media Informatics

Nowadays the development of the processors is going through changes, in the future there will be a great tone on the parallelization of the applications. The primary score behind this metamorphosis, that the clock frequency of the processors cannot be raised anymore, because of some technological and physical reasons. Therefore the manufacturers are reconsidering the basic architectures and making effort on the development. One of the promising approaches is to increase the number of the cores on one chip. Besides the common processors that are working in the personal computers, there are now a lot of chips with 32, 64 or even more cores. As long as we have to wait for the breakthrough in the technology area, which would make it possible to increase further the clock frequency, we also have to use and develop the many-core processors.

To utilize the advantages, that the several cores are offering, it is very important to divide our application to modules, which are able to run simultaneously on different cores. So we have to apply a different approach, aspect in the software development as well. Of course almost every program is unique, and the parallelization method always depends on the current application’s characteristic. For example in telecommunication we are frequently using packet processing applications, where we have to run the same procedures for the great number of similar packets. In this case it is quite easy to cut up the application. On the other hand when we would like to do the same with a complex signal processing algorithm, we would find ourselves in a really difficult situation.

With farseeing software design it is possible to achieve better system performance with the same costs. Of course it is necessary to study the architecture of the current processor and use the special communication features offered.

The aim of this thesis is to implement an IP packet processing framework on a Tilera Tile64 processor. As base for the software we are using an Ericsson research project. We are focusing on the packet control system, and we would like to split it between the cores. The long term goal of the project is to create a packet processing application which adapts to the current traffic, and handles dynamically the incoming packets. It is also important to take care of the energy consumption and make it efficient. This means that the individual cores can be switched on/off according to the momentary traffic.

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