Integrated OOK radio receiver design

OData support
Supervisor:
Fehér Gábor
Department of Broadband Infocommunications and Electromagnetic Theory

Amplitude Shift Keying (ASK) is a popular modulation technique used in digital data communication for a large number of low-frequency RF applications. A further simplification of the ASK method is On-Off Keying (OOK) modulation. OOK communication protocol is commonly used in short-range wireless applications, where the low power consumption is one of the most important parameters, especially popular in battery-operated portable applications.

In this work I made the system level design of an integrated CMOS OOK receiver, where I chose the architecture, I made the related specifications, and I designed the circuits too.

The receiver operates in the 300 and 434MHz Industrial Science and Medical (ISM) bands, the specifications are related to the FCC and ETSI organizations, these regulations are summarized at the beginning of this thesis. I have researched some already available CMOS single-chip solutions, which can operate in these ISM bands with OOK modulation, those main parameters are summarized. After these I reviewed the basic properties of the OOK modulation, the modulation method, the spectra, the effect of the noisy channel and the requirements of the demodulation.

Related to the regulations, the available solutions and the modulation I analised the possible receiver architectures in details, those advantages and disadvantages and I made some precalculations according to the viability.

For the receiver's system plan I chose the lowest cost and power hungry architecture. Regarding to the available chips and regulations I designed the specifications, taking the technology into account I tried to optimalize. The used up equations for the block parameters are summerized in a separate chapter, and I used these in an EXCEL table. The table is attached to this work.

After these I present the choosed circuits, explain the working and the reasons of the existence in details. Those operability are verified with different simulations in typical case and in worst case corners too, the simulation results are summarized. The testbenches and the schematics with the exact values of the instances are attached to this work as appendix.

I used Cadence 6.1 IC designer software with 180nm CMOS technology provided by the Microchip Technologies Hungary Kft.

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