My objective was to implement a framebuffer based on SDRAM, to facilitate the implementation of image processing functions of the EDICAM intelligent camera. EDICAM (Event Detection Intelligent Camera) is a high-speed digital camera for diagnostic applications in the field of plasma physics. The goal was to develop a memory controller, which is able to store images to DDR2 memory taken by the EDICAM. The task was accomplished using the FPGA chip located in the EDICAM. After studying the system, I examined the applied hardware thoroughly to take all possibilities into consideration of implement the framebuffer. With the acquired information I was able to create the high level specification of the framebuffer. I created the system level design, and designed the sub modules of the framebuffer, implemented the framebuffer in VHDL based on the specification. The implemented system was subjected to low-level tests and measurements, and user-level tests also. To present the most important features of the framebuffer, I created a demonstration. The implementation of the framebuffer was successful, the presence of the framebuffer increased the flexibility of the EDICAM firmware, allowing new features to be implemented.