Modeling and verification of industrial communication system

OData support
Supervisor:
Dr. Fehér Béla
Department of Measurement and Information Systems

My essay is describing a topic of increasing popularity and spread in the hardware design world, namely the creation and verification of high level hardware models.

Creating a high level model can benefit the process of the hardware design in numerous ways. Such a model is functionally equivalent to the designed hardware, but the implementation of the functionality and its interfaces are not described on RTL (Register-Transfer Level), but rather on a higher level of abstraction. In such a way, the functionality of the hardware can be implemented and simulated as fast as possible, which enables the opportunity of tryout and analysis of various different implementations. My essay describes the process and benefits of creating such a model. I choose SystemC as the language of my model, because it was created specifically for such a purpose and it is widespread in the industry. In my essay I also describe this language, concentrating on its aspects of which modeling benefits the most.

The verification (testing of functionality) of logical designs has significantly improved in the last years. The HDL testbenches (which were initially used) have been replaced by verification environments at most companies. With the help of these checking of functional correctness has got more effective and measurable. The measurability of this process is very important for the evaluation of the necessary effort and the deadlines of the project.

It is very important to use some kind of methodology in the verification, which can make the process more efficient and repeatable. Nowadays UVM is the most widespread of such methodologies. I designed my verification environment according to its rules and recommendations. Describing my environment, I also describe the regarding instructions of the UVM. Moreover, my verification environment illustrates the practical use of this methodology.

I also describe the different ways of connecting the model and the verification environment. This area is not yet fully integrated in verification languages, because historically the verification was always performed on an HDL design.

The reader of this essay will get an overall picture of those processes and methodologies of hardware design which are rarely known to engineers of other areas, but are essential to a professional hardware design process.

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