JTAG based SoC tester

OData support
Supervisor:
Lazányi János Gyula
Department of Measurement and Information Systems

The main goal of this BSc thesis is to implement a function library for WishBone

peripherals using JTAG Live software. Boundary scan testing became necessary during

the 1980s when BGA packaging got popular. Boundary scan is a testing method for

printed circuit boards. In the thesis I demonstrate the basic architecture of a boundary

scan enabled device, and the process of boundary scan testing.

As a target device I was using a Digilent Spartan 3E FPGA Starter board. The

WhisBone bus itself is the part of a softcore System on Chip that is based on an OpenRISC

open source CPU. This SoC is called Minimal OpenRISC System on Chip (short:

minsoc).

The minsoc includes a debug system called Advanced Debug System which is

designed for downloading code to the target CPU in a System-on-Chip, and perform

source-level debugging of the firmware. This design includes a hardware interface which

directly connects to the CPU and the WishBone bus. The original debug system includes

a PC-side software (Advanced JTAG Bridge) that controls the JTAG cable and also

communicates with the GNU debugger. This software is replaced with the script written

in Python.

The function library includes basic control functions for the Advanced Debug

Interface and also some for the peripherals like read and write functions. These functions

are tested on an on-chip memory, and on an open source GPIO IP core. The IP core is

connected to the WishBone bus and controls the LEDs on the developer board.

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