Nowadays, the most popular interface of the high resolution cameras is the MIPI CSI2 used basically in mobile industry. It can provide even FullHD video signal. The off-the-shelf embedded devices often do not allow using MIPI. However, FPGAs give appropriate support to create this interface. Furthermore fast and parallel data processing is also well achievable.
The goal of my thesis is to realize MIPI CSI2 on a development board that contains a Xilinx Spartan-6 FPGA. After detailed understanding of standard it contains the modular design of interface and its implementation in Verilog hardver description language.
The Ov6547 camera module, which used in the task operates with the most widespread Bayer pattern. The output signal produced by camera is a raw image information processed by a color filter.
Preparing my thesis a microprocessor system based on MicroBlaze shall be created that contains the needed I2C periphery to configure the camera module. After the configuration system, a color filter module shall also be created that allows production of colorful image connected to the output of MIPI.
To connect a DVI transmitter module to the filter output is also required. It enables the visualization of the produced image.