The transformation procedures used in image compression standards play an important role in the field of image processing. For instance the discrete cosine transform, which is used by the JPEG standard or the discrete wavelet transform of JPEG 2000. The execution of these transformations are restricted to a small amount of time in real-time applications. Therefore, the acceleration of these transformations by hardware becomes essential when we use high resolution image data.
The FPGA (Field Programmable Gate Array) is an ideal hardware for accelerating an application specific transformation in a cost efficient way. Furthermore, an excellent developement device to make a fast changing prototype by reason of its reprogrammable nature.
In my thesis I examine the JPEG 2000 standard based on the discrete wavelet transformation, then I review the mathematical basics of wavelet transformation in order to get a deeper understanding of it and search for an efficient algorithm as well.
I seek for a solution to implement the chosen algorithm on the FPGA device considering the efficient utilization of its resources. Thenceforth I present the designed system and its components.
After that, I verify the operability of each component and the entire system. Finally I summarize the results of the thesis and share the possible further development of the hardware too.