My thesis was about the design of a low power voltage comparator. Both the design of the schematics and layout were part of my thesis.
Beside of the study of necessary literature I have proposed a schematic that is capable of interfering in an architecture situated in sleep mode if the necessary event occurred. I have designed from the basics the schematics of the comparator and by multiple simulations I have managed to gain an optimized architecture. The power consumption of my architecture is comparable with the one of a microcontroller in sleep mode. During my work I have used the Caedance designing software to create the schematics and by simulations I have presented and proved the usability and functionality of the comparator that I have designed.
The thesis insight into the world of analog circuit design, and a coupling implemented, which performs a very fast and low-power comparator function. During the implementation, I chose not to latch-based finish, which is usually a low-power comparators starting point, but requires a clock signal. In contrast, the coupling of a differential amplifier circuit I based and reflects the scope of this made it to the final design. I checked the need for an additional inverting stage. The resulting circuit has a low offset voltage. In its current comparator reference circuit also built, which meets the comparator bias current. The design and analysis of multiple simulations were undertaken on the basis that, if necessary, modified and optimized the circuit. I designed the physical implementation of the circuit in the wiring diagram. I checked this agreement on the basis of the error-free layout of the circuit diagram identifikálva the parasitic effects.
The designed circuit should have been constructed and the final elements perform additional tests to verify the design and simulation results in real operation. This feedback could be used as a comparator in terms of further optimization.