Our everyday life depends on a variety of complex computing equipment. The growth of complex communication and information systems requires intense testing of hardware and software components.
Due to the rising density of our digital systems, designing these circuits by hand is no longer efficient. Along with the appearance of hardware description languages (Verilog, VHDL, SystemC) testing the application-specific integrated circuits and programmable logic devices such as FPGAs is becoming more important.
Verifying the correct functionality of a complex structure makes up to seventy percent of the development. Thus today’s verification and validation (V&V) of compact systems of millions of gates is becoming a new critical bottleneck in design flow.
In the first part of my thesis I introduce Programmable Logic Devices (PLDs) and the available verification tools. Then I construct the verification environment of the specified unit. Finally I summarize the results of the simulation and implement additional circuits to fix bugs in the system.