The topic of my thesis is about implementing a 64-bit floating-point arithmetic unit using an FPGA, in which I give a brief review about the structure of an FPGA and also about floating-point numbers in IEEE standards as well as their basic operations.
Most of the algorithms, implemented in FPGA based systems, initially relied on the use of integer or fixed-point numbers. Resorting to floating-point representation gives the possibility of a wider dynamic range for computations, which makes the operations and the results more accurate. However there is a great disadvantage in the number of required resources, because involving floating-point operations takes significantly more and complicated hardware. With the current improvements in FPGA systems, developers are increasingly taking advantage of the opportunities provided by FPGAs as a platform for floating-point implementations.
Considering the written above, my primary goal is to describe and implement the four basic floating-point operations using Verilog HDL, and also to speed up the process by using a pipelined structure. This is followed by monitoring the implemented unit’s behavior in a simulated environment and after that on a real FPGA based development board. It is important to create a structure that ensures the provision of future development opportunities, such as implementing a performance efficient expansion for operation sequences.