In the present days, FPGA (Field Programming Gate Arrays) circuits become increasingly used in the area of High Performance Computing. Although these circuits’ built-in resources provide many opportunities for the efficient realization of many arithmetic tasks, but the mapping of high-precision floating-point operations still requires too many FPGA resources. The built-in multiplier and DSP modules are getting better support for these arithmetic operations, but there is still an active research and development in this area for even better solutions and algorithms.
The first aim of this Diploma Thesis work is the review of this area, including the IEEE 754 Floating-point standard, the solutions offered by the manufacturers, the available technical tools in block level system design and in high level synthesis. I would like to supplement this overview with the introduction of the Floating-point arithmetical unit developed in the diploma work. The second aim is the presentation of the potential of the described technology through the implementation of an exemplary design, and I also would like to complement these experiences with the implementation parameters. Last, but not least, I will give an assessment of the opportunities in the area, based on my experiences.